Reference is made to FIG. 1 showing a prior art single photon avalanche diode (SPAD) 100 (see, also, United States Patent Application Publication No. 2013/0193546, incorporated by reference). The SPAD 100 is formed in an epitaxial semiconductor layer 102 grown on a semiconductor substrate 104. The layer 102 and substrate 104 may, for example, be doped with a p-type dopant. The p-type dopant exhibits a dopant concentration gradient such that the epitaxial semiconductor layer 102 is more heavily doped towards and closer to the semiconductor substrate 104 and more lightly doped towards and closer to a top surface 106. A deep well 110 is implanted in the epitaxial semiconductor layer 102 and is covered with a shallow well 112. The wells 110 and 112 are doped, for example, with an n-type dopant. The well 112 includes an implant of a heavily doped electrode 116 forming the cathode terminal of the SPAD 100. The electrode 116 is doped, for example, with an n-type dopant. A region 120 of the epitaxial semiconductor layer 102 forms a guard ring surrounding the wells 110 and 112. A well 124 is implanted in the epitaxial semiconductor layer 102 surrounding the guard ring region 120. The well 124 is doped, for example, with a p-type dopant. The well 124 includes an implant of a heavily doped electrode 126 forming the anode terminal of the SPAD 100. The electrode 126 is doped, for example, with a p-type dopant. A shallow trench isolation (STI) structure 128 is provided in the well 124. The SPAD 100 includes a multiplication junction 130, where avalanche breakdown occurs during use, that is located at the PN junction between the p-type doped epitaxial semiconductor layer 102 and the n-type doped deep well 110.
FIG. 2 is a schematic diagram of a read out circuit 200 for the SPAD 100 of FIG. 1. The circuit 200 includes a quench resistor 202 coupled in series with the SPAD 100. More specifically, one terminal of the resistor 202 is coupled to a high supply voltage node 204 and the other terminal of the resistor 202 is coupled at node 206 to the cathode terminal of the SPAD 100. The anode terminal of the SPAD is coupled to a ground reference voltage node 208. The high positive breakdown voltage VBD at the high supply voltage node 204 is not compatible with standard CMOS transistor gates. Thus, the node 206 cannot be directly connected to the input of the CMOS inverter circuit 212. An AC coupling capacitor 216 is provided with one capacitor plate coupled to node 206 and the other capacitor plate coupled to the CMOS inverter circuit 212 input. A bias transistor 220 is coupled between a bias supply voltage (VDD) node 224 and the input of the CMOS inverter circuit 212. The bias transistor 220 may, for example, comprise a p-channel MOSFET with gate and source terminals coupled to the bias supply voltage node 224 and a drain terminal coupled to the CMOS inverter circuit 212 input.
With the SPAD 100 of FIG. 1 in the circuit 200 of FIG. 2 it will be noted that the anode terminal of the SPAD 100 is formed by the integrated circuit chip substrate layers 102 and 104 which is grounded 208. In this configuration, the SPAD 100 cannot be turned off and accordingly presents a load to the high positive breakdown voltage VBD at the high supply voltage node 204.